An example of a liquid crystal display device which has a γ characteristic with a reduced viewing angle dependence is a liquid crystal display device which employs a multi-pixel driving method. Multi-pixel driving is carried out with use of pixels each made up of at least two sub-pixels having luminances different from each other. As such, the multi-pixel driving achieves an improved viewing angle characteristic, that is, a γ characteristic with a reduced viewing angle dependence.
FIG. 7 illustrates an example configuration of a pixel included in a liquid crystal display device which employs the multi-pixel driving method (see, for example, Patent Literature 1).
The pixel P is divided into two sub-pixels sp1 and sp2. The sub-pixel sp1 includes: a TFT 16a; a sub-pixel electrode 18a; and a storage capacitor 22a. The sub-pixel sp2 includes a TFT 16b; a sub-pixel electrode 18b; and a storage capacitor 22b. 
The TFTs 16a and 16b have (i) respective gate electrodes both connected to an identical gate bus line GL and (ii) respective source electrodes both connected to an identical source bus line SL. The storage capacitor 22a is formed between the sub-pixel electrode 18a and a storage capacitor bus line CsL1. The storage capacitor 22b is formed between the sub-pixel electrode 18b and a storage capacitor bus line CsL2. The storage capacitor bus line CsL1 is provided so as to extend in parallel to gate bus lines GL and so as to be separated from the above-mentioned gate bus line GL by a region of the sub-pixel sp1. The storage capacitor bus line CsL2 is provided so as to extend in parallel to the gate bus lines GL and so as to be separated from the above-mentioned gate bus line GL by a region of the sub-pixel sp2.
For each pixel P, (i) the storage capacitor bus line CsL1 serves also as a storage capacitor bus line CsL2 with which a storage capacitor 22b is formed by the sub-pixel sp2 of a pixel P that is adjacent to the pixel P across the storage capacitor bus line CsL1, and (ii) the storage capacitor bus line CsL2 serves also as a storage capacitor bus line CsL1 with which a storage capacitor 22a is formed by the sub-pixel sp1 of a pixel P that is adjacent to the pixel P across the storage capacitor bus line CsL2.
With reference to FIGS. 8 and 9, the following description deals with a method for driving the storage capacitor bus lines CsL1 and CsL2 included in a display panel which employs the multi-pixel driving method.
As illustrated in FIG. 8, the storage capacitor bus lines CsL (referring collectively to the storage capacitor bus lines CsL1 and CsL2) are (i) provided alternately in an active area AA, that is, a display region, and (ii) connected to CS trunk lines bb provided in regions adjacent to the active area AA. A plurality of the CS trunk lines bb form a CS trunk line group BB. The CS trunk lines bb are provided so that a single CS trunk line group BB is formed only in a first region (that is, only in one of the adjacent regions) which is adjacent to the active area AA on a predetermined side of a first direction in which the storage capacitor bus lines CsL extend. The predetermined side is a side on which a first end of each of the storage capacitor bus lines CsL is present. Alternatively, the CS trunk lines bb are provided so that a CS trunk line group BB is formed in each of (i) the first region and (ii) a second region (that is, in each of the adjacent regions) which is adjacent to the active area AA on a side of the first direction. The side is a side on which a second end of each of the storage capacitor bus lines CsL is present.
In the case where a single CS trunk line group BB is provided only in one of the adjacent regions, the first end, present on the predetermined side, of each of the storage capacitor bus lines CsL is connected to a CS trunk line bb. In the case where a CS trunk line group BB is provided in each of the adjacent regions, (i) the first end, present on the predetermined side, of each of the storage capacitor bus lines CsL is connected to a CS trunk line bb provided in the region which is adjacent to the active area AA on the side on which the first end is present, whereas (ii) the second end of each of the storage capacitor bus lines CsL is connected to a CS trunk line bb provided in the region which is adjacent to the active area AA on the side on which the second end is present. The CS trunk lines bb extend in a second direction orthogonal to the first direction in which the storage capacitor bus lines CsL1 and CsL2 extend, the second direction being a direction in which the source bus lines SL extend.
FIG. 8 illustrates an example case in which a CS trunk line group BB made up of 12 CS trunk lines bb is provided in each of the adjacent regions. The storage capacitor bus lines CsL are each connected to (i) a CS trunk line bb of one of the CS trunk line groups BB and (ii) a CS trunk line bb of the other of the CS trunk line groups BB. Specifically, 12 storage capacitor bus lines CsL (the number 12 being equal to the number n [where n is an even number] of CS trunk lines bb which make up each CS trunk line group BB) provided next to one another are connected to respective CS trunk lines bb of each of the CS trunk line groups BB. Each set of 12 (that is, n) storage capacitor bus lines are connected the CS trunk lines bb as such.
In the case where a single CS trunk line group BB is provided only in one of the adjacent regions, n storage capacitor bus lines CsL provided next to one another are connected to respective CS trunk lines bb of the CS trunk line group BB. Each set of n storage capacitor bus lines are connected to the CS trunk lines bb as such.
Both in the case where a single CS trunk line group BB is provided only in one of the adjacent regions and in the case where a CS trunk line group BB is provided in each of the adjacent regions, n storage capacitor bus lines CsL provided next to one another are supplied with respective storage capacitor voltages illustrated in FIG. 9. On each odd-numbered line, a pair of storage capacitor bus lines CsL1 and CsL2 corresponding to the sub-pixels sp1 and sp2 of a pixel P are supplied with storage capacitor voltages Vcs (indicated by Vcs1, Vcs2 . . . in FIG. 9) having respective binary waveforms which are switched in level at identical timing and which oscillate through an identical cycle period. Such pairs of storage capacitor voltages Vcs are provided in a number of n/2 such that the pairs have respective phases which are gradually shifted from one odd-numbered line to the next. Gate pulses Vg (indicated by Vg1, Vg3 . . . in FIG. 9) for the respective odd-numbered lines each have a pulse period which corresponds to a period of corresponding storage capacitor voltages Vcs during which period respective values of the corresponding storage capacitor voltages Vcs are constant. The pulse period ends at the rise or fall of each corresponding storage capacitor voltage Vcs.
With the above arrangement in use, data signals are first written to the pixels P on the odd-numbered lines. After the data signals are written, the storage capacitor voltages Vcs are changed. While an identical data signal is written to the two sub-pixels sp1 and sp2 of a pixel P, the above change causes different potential shift amounts ΔV to be added to the respective potentials of the pixel electrodes of the two sub-pixels sp1 and sp2. This is due to a feed-through phenomenon via a capacitance between the gate bus line GL and each pixel electrode. As a result of the above addition, the sub-pixels sp1 and sp2 are different from each other in luminance. As such, an average luminance corresponding to an effective voltage applied across the liquid crystal layer through one frame period of the storage capacitor voltages Vcs is suitable over a wide viewing angle in terms of a γ characteristic for the pixels P as a whole.
When the even-numbered lines are scanned after the odd-numbered lines are scanned, storage capacitor voltages Vcs applied to the sub-pixels sp1 and sp2 of each pixel P form a pair of voltages which are switched in level not at identical timing between the odd-numbered lines and the even-numbered lines. However, the pixel electrodes on the even-numbered lines each have a potential whose first change after the end of a corresponding gate pulse is similar to that for the odd-numbered lines. This also indicates an improved γ characteristic.
Note that the above description merely exemplifies the respective waveforms of the storage capacitor voltages Vcs and the manner of line scanning. A main feature of this technique is rather the following: The sub-pixels sp1 and sp2 of a pixel P are caused to be different from each other in luminance with use of changes in the respective storage capacitor voltages Vcs, the changes being different from one another, so that the γ characteristic of the pixels P as a whole is improved.
The storage capacitor voltages Vcs are each supplied to a storage capacitor bus line CsL via a corresponding CS trunk line bb. The CS trunk lines bb of each CS trunk line group BB are thus supplied with storage capacitor voltages Vcs which are different from one another. It follows that a CS driver (not shown) supplies, to each CS trunk line group BB, a number of storage capacitor voltages Vcs having respective phases different from one another, the number being equal to the number of the CS trunk lines bb in the CS trunk line group BB. FIG. 9 illustrates an example case in which storage capacitor voltages Vcs having 12 phases are supplied (the first 10 phases of the storage capacitor voltages Vcs 1-Vcs10 being illustrated). Further, in the case where a CS trunk line group BB is provided in each of the regions adjacent to the active area AA as illustrated in FIG. 8, an identical storage capacitor voltage Vcs is applied to two CS trunk lines bb each included in one of the CS trunk line groups BB, the two CS trunk lines bb being connected to an identical storage capacitor bus line CsL. In the case where a storage capacitor voltage Vcs is, as described above, supplied from both of the regions adjacent to the active area AA, it is possible to prevent, on a large liquid crystal display screen, such a storage capacitor voltage Vcs from having a waveform which is different depending on a location in the active area AA due to an interconnect delay.